Les interruptions TMR0-RB0-RB du microcontrôleur 16F84 et 16F877:
- Exemple interruption RB0: TP: interruption RB0: moteur 2 sens de rotation avec interruption de 1000ms
2. Exemple interruption RB4:
3.Exemple interruption TIMER0:
4. INTERRUPTION TIMER O :JEUX DE LUMIERE
5. Projet Horloge:Inerruption TMRO
6. Rappel de cours
Le PIC 16F84A dispose de 4 sources d’interruptions :
Interruption sur la broche RB0/INT
Interruption « RB » : sur changement du niveau logique d’au moins une de ces 4 broches : RB4, RB5, RB6 ou RB7 (port B)
Interruption de débordement du registre TMR0 (H’FF’ -> H’00’)
Interruption de fin d’écriture de l’EEPROM
RBPU – Port B Pull up Enable bit.
1 – PortB pull-ups are disabled.
0 – PortB pull-ups are enabled.
INTEDG – Interrupt Edge Select bit.
1 – Interrupt on rising edge of RB0/INT pin.
0 – Interrupt on falling edge of RB0/INT pin.
T0CS – TMR0 Clock Source Select bit.
1 – Transition on TOCKI pin.
0 – Internal instruction cycle clock (Fosc/4).
T0SE – TMR0 Source Edge Select bit selects pulse edge (rising or falling) counted by the timer TMR0 through the RA4/T0CKI pin.
1 – Increment on high-to-low transition on TOCKI pin.
0 – Increment on low-to-high transition on TOCKI pin.
PSA – Prescaler Assignment bit assigns prescaler (only one exists) to the timer or watchdog timer.
1 – Prescaler is assigned to the WDT.
0 – Prescaler is assigned to the TMR0.
PS2, PS1, PS0 Prescaler Rate Select bits Prescaler rate is selected by combining these three bits. Described, as shown in the table below, prescaler rate depends on whether prescaler is assigned (TMR0) or
GIE – Global Interrupt Enable bit – controls all possible interrupt sources simultaneously.
1 – Enables all unmasked interrupts.
0 – Disables all interrupts.
PEIE – Peripheral Interrupt Enable bit acts similar to GIE, but controls interrupts enabled by peripherals. It means that it does not affect interrupts triggered by the timer TMR0 or by changing state on port B or RB0/INT pin.
1 – Enables all unmasked peripheral interrupts.
0 – Disables all peripheral interrupts.
T0IE – TMR0 Overflow Interrupt Enable bit controls interrupt enabled by TMR0 overflow.
1 – Enables the TMR0 interrupt.
0 – Disables the TMR0 interrupt.
INTE – RB0/INT External Interrupt Enable bit controls interrupt caused by changing logic state on pin RB0/IN (external interrupt).
1 – Enables the INT external interrupt.
0 – Disables the INT external interrupt.
RBIE – RB Port Change Interrupt Enable bit. When configured as inputs, port B pins may cause interrupt by changing their logic state (no matter whether it is highto- low transition or vice versa, fact that something is changed only matters). This bit determines whether interrupt is to occur or not.
1 – Enables the port B change interrupt.
0 – Disables the port B change interrupt.
T0IF – TMR0 Overflow Interrupt Flag bit registers the timer TMR0 register overflow, when counting starts from zero.
1 – TMR0 register has overflowed (bit must be cleared in software).
0 – TMR0 register has not overflowed.
INTF – RB0/INT External Interrupt Flag bit registers change of logic state on the RB0/INT pin.
1 – The INT external interrupt has occurred (must be cleared in software).
0 – The INT external interrupt has not occurred.
RBIF – RB Port Change Interrupt Flag bit registers change of logic state of some port B input pins.
1 – At least one of the port B general purpose I/O pins has changed state. Upon reading portB, RBIF (flag bit) must be cleared in software.
0 – None of the port B general purpose I/O pins has changed state.